Fractional-N frequency synthesizers can be used to overcome many limitations associated with integer-N frequency synthesizers. In fractional-N frequency synthesizers, the effective frequency divide ratio is a fractional number, which enables a relatively high frequency reference signal to be used to achieve fine resolution of frequencies in synthesizer output signals. This fractional number is typically achieved by periodically changing an integer divide ratio so that a desired fractional number can be approximated. One typical disadvantage associated with fractional-N frequency synthesis is the generation of unwanted low-frequency “spurs” by a dual-modulus (or multi-modulus) divider. These spurs make fractional-N frequency synthesizers impractical for many applications unless they are suppressed to a negligible level. Conventional spur reduction techniques include: (i) digital-to-analog (DAC) phase estimation, (ii) random jittering, which randomizes a divide ratio, (iii) sigma-delta (ΣΔ) noise shaping, which modulates a divide ratio, (iv) phase interpolation; and (v) pulse generation. Some of these spur reduction techniques are disclosed in articles by: S. Pamarti et al., entitled “A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs”, IEEE Trans. on Circuits and Systems, Vol. 55, No. 6, pp. 1639-1647, July (2008); and Li Zhang et al., entitled “A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 2922-2934, November (2009).
As illustrated by FIG. 1A, a frequency synthesizer 10 may include a fractional-N divider 12 within a feedback path of a phase-locked loop (PLL), which filters jitter in the output of the divider 12. This fractional-N divider 12 may operate by modulating between two or more integer values. The phase-locked loop of FIG. 1A contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20. This VCO 20 generates an output signal having a frequency that is a non-integer multiple of the frequency of the input reference signal. An integer divider 22 may also be provided for generating an output signal at a reduced frequency relative to the VCO output signal. Examples of the frequency synthesizer 10 of FIG. 1A are disclosed at U.S. Pat. No. 7,532,081 to Partridge et al., entitled “Frequency and/or Phase Compensated Microelectromechanical Oscillator,” and FIG. 3 of U.S. Pat. No. 7,417,510 to Huang, entitled “Direct Digital Interpolative Synthesis”.
FIG. 1B illustrates a frequency synthesizer 10′, which includes an integer divider 12′ within a feedback path of a phase-locked loop (PLL). This phase-locked loop contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20, which generates an output signal having a frequency that is an integer multiple of the frequency of the input reference signal. Multiple fractional-N dividers 22a-22d may be provided for generating output signals having different frequencies, which do not have integer relationships with the output frequency of the VCO 20. As will be understood by those skilled in the art, additional circuitry may be needed to reduce jitter in the signals generated by the dividers 22a-22d. The dividers 22a-22d may be provided as interpolative dividers as disclosed at FIGS. 4-6 of the '510 patent to Huang. For example, as shown by FIG. 5 of Huang, an interpolative divider can include a fractional-N divider, which receives a VCO clock. A first order delta sigma modulator receives a digital divide ratio (M/N). The integer portion of the digital divide ratio is supplied to the fractional-N divider as a divide control signal, which can be a stream of integers that approximate the fractional divide ratio. A digital quantization error, which corresponds to the fractional portion of the divide ratio, is supplied to a digitally controlled phase interpolator. The jitter introduced by the fractional-N divider can be canceled by interpolation in the phase interpolator, which is based on the digital quantization error supplied by the delta sigma modulator. In this manner, the input clock from the VCO is first divided down by the fractional-N divider according to the control information provided by the delta sigma modulator and then the phase interpolator operates to cancel quantization errors in the output of the fractional-N divider.
Additional examples of fractional-N frequency synthesizers, which utilize an accumulator within a numerically-controlled oscillator and a phase interpolator, are disclosed at FIG. 6 of the '510 patent to Huang and in U.S. Pat. No. 7,724,097 to Carley et al., entitled “Direct Digital Synthesizer for Reference Frequency Generation.” Digitally-controlled oscillators containing interpolative dividers are also disclosed in U.S. Pat. No. 8,441,291 to Hara et al., entitled “PLL Using Interpolative Divider as Digitally Controlled Oscillator,” and U.S. Pat. No. 8,248,175 to Hara, entitled “Oscillator with External Voltage Control and Interpolative Divider in the Output Path.” In addition, U.S. Pat. No. 8,692,599 to Gong et al., entitled “Interpolative Divider Linearity Enhancement Techniques,” discloses a clock synthesizer that utilizes a phase interpolator calibration signal, which is based on an error signal indicative of phase interpolation error.
Still further examples of fractional-N frequency synthesizers are disclosed in commonly assigned U.S. Pat. No. 8,559,587 to Buell et al., entitled “Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators,” the disclosure of which is hereby incorporated herein by reference. In particular, in FIGS. 2A-2B of the '587 patent, a fractional-N divider circuit 100 is illustrated as including a multi-modulus divider 102, which is configured to perform at least /N and /N+1 frequency division of a first reference signal (REFHF) received at a first input thereof, where N is an integer greater than one. This multi-modulus divider 102 selectively performs a /N and /N+1 division according to a value of an overflow signal (OVERFLOW) received at a second input thereof. This overflow signal is generated by a divider modulation circuit and phase error calculator 104, which is shown as the divider modulation circuit 104a and the phase error calculator 104b. In particular, the overflow signal is generated in response to a digital code that specifies the sequence of division moduli to be used by the multi-modulus divider 102 when performing the /N and /N+1 frequency division of the first reference signal REFHF.
The divider modulation circuit and phase error calculator 104 of FIG. 2A includes an accumulator 106 having multiple serially-cascaded accumulator segments 106a-106n therein. These segments 106a-106n generate a corresponding plurality of segments of a count value having at least one period of clock latency therebetween, in response to corresponding bits (LSB, . . . , MSB) of a digital code and corresponding segment overflow signals. The segments 106a-106n may be synchronized with a clock signal, which is shown as a signal (f1) generated by the divider 102. For example, a relatively wide 16-bit segmented accumulator, which is typically needed for high resolution, may be defined by a cascaded arrangement of four 4-bit accumulator segments. The segmented accumulator 106 may provide advantages over typical accumulators within conventional delta-sigma modulators because the per cycle delay through the divider modulation circuit 104a is equivalent to the delay through a single segment (106a, . . . , 106n) of the accumulator 106, which may need to run at twice a frequency of an output signal (e.g., FOUT). In this manner, the segments of the accumulator 106 operate collectively as an adder with at least one cycle (and typically many cycles) of latency. This segmented “adder” does not generate accurate counts with each clock signal, but ultimately yields a correct, albeit delayed, sequence of final overflow signals (from segment 106n) at a potentially much higher frequency rate. As further illustrated by FIG. 2A, the phase error calculator 104b includes a segment (e.g., four-bit) delay block 105a that compensates for the latency between the accumulator segment values associated with segments 106n-1 and 106n. An additional accumulator segment 107 and delay block 105b, which are optional, may be used within the phase error calculator 104b to produce a delta-sigma modulated signal that represents the value in the lower accumulator segments that do not directly feed a phase correction circuit 110.
This phase correction circuit 110 is configured to generate a second reference signal (FOUT) in response to the divider output signal (f1) generated by the multi-modulus divider 102. The phase correction circuit 110 includes a D-type flip-flop 112, which has a data terminal responsive to the second reference signal FOUT and a synchronization terminal responsive to the divider output signal f1, and a pulse-width locked loop 114. This pulse-width locked loop 114 may include, among other things, an analog phase interpolator and a digital phase selection circuit, as shown by FIG. 2B.
The phase correction circuit 110 is illustrated as including a pulse-width locked loop 114 that utilizes a delay line containing a plurality of voltage-controlled delay cells 116a-116e to achieve a delay of one VCO period and an additional VCO cell 116f to provide equivalent loading. The pulse-width locked loop 114 further includes an XOR gate 118, which operates as a pulse generator to generate a pulse having a width of four delay blocks from the delay line, a charge pump 120 and capacitive loop filter CL. As shown by the four inputs to each of the pair of multiplexers 122a-122b, digital phase selection in fine steps of TVCO/4 can be achieved with analog phase interpolation being performed between these finer steps by an output multiplexer 124. This configuration yields two (2) bits of resolution allocated to the multiplexers and additional bits of resolution in the analog phase interpolator. Although not wishing to be bound by any theory, because the edges of the signals provided to the phase interpolator are closely spaced, they typically do not need to be filtered. The close spacing may also yield greater linearity and preclude any need for trimming.
Referring now to FIG. 3, another conventional fractional-N divider circuit 100′ is shown as including a multi-modulus divider 102, which is configured to perform at least /N and /N+1 frequency division of a first reference signal (REFHF) received at a first input thereof, where N is an integer greater than one. This multi-modulus divider 102 selectively performs a /N and /N+1 division according to a value of an overflow signal (OVERFLOW) received at a second input thereof. This overflow signal is generated by a divider modulation circuit and phase error calculator 104. In particular, the overflow signal is generated in response to a digital code that specifies the sequence of division moduli to be used by the multi-modulus divider 102 when performing the /N and /N+1 frequency division of the first reference signal REFHF.
The divider modulation circuit 104a includes an accumulator 106 having multiple serially-cascaded accumulator segments 106a-106n therein. These segments 106a-106n generate a corresponding plurality of segments of a count value having at least one period of clock latency therebetween, in response to corresponding bits (LSB, . . . , MSB) of a digital code and corresponding segment overflow signals. The phase error calculator 104b includes a plurality of delay elements 105a-150b and an additional accumulator segment 107, which collectively generate multiple bits of a digital phase error that is provided to a phase correction circuit 110′. The accumulator segments 106a-106n and 107 are synchronized with a high frequency clock signal, which may be generated by a frequency multiplier 109.
This phase correction circuit 110′ is configured to generate a second reference signal (FOUT) in response to a divider output signal (f1) generated by the multi-modulus divider 102. The phase correction circuit 110′ is configured so that the second reference signal (FOUT) has a substantially jitter-free and uniform duty cycle. The phase correction circuit 110′ is illustrated as including a pair of latches (e.g., D-type flip-flops) 112a-112b, which have data terminals responsive to the second reference signal FOUT and synchronization terminals (e.g., clock terminals) responsive to true and complementary versions of the divider output signal f1, which operates as a duty cycle adjustment circuit, and an analog phase interpolator 114′. This phase interpolator 114′ may be configured as an analog multiplexer, which combines two edges of the signals generated by the flip-flops 112a-112b that are separate by one VCO period. Programmable filters 117a-117c are also provided for adjusting the edge rates of the input and output signals and, therefore, the linearity of the analog phase interpolator 114′.